An enhanced technique for simulating short-circuit power dissipation

A circuit-simulation technique which permits the measurement of the average short-circuit power dissipation component in integrated circuits using SPICE is presented. It is an extension of a previously presented scheme by S.M. King (see ibid., vol.21, no.5, p.889-91, 1986) which measures average power dissipation while circuits are being simulated. The extended technique is most appropriate for low-power circuit design. It can be applied effectively to any complementary circuit structure, such as CMOS, that does not permit current flow (other than leakage current) during steady-state operation. Results for differently W/sub p//W/sub n/ ratioed W/sub p//W/sub n/ CMOS circuits are shown.<
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