A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set

A 12:1 multiplexer and 11:2 demultiplexer that operate at up to 3 Gb/s are discussed. The circuits were fabricated with a 1- mu m-design-rule silicon NMOS VLSI technology and operate from a 3.5-V power supply. The multiplexer chip has 200 gates and dissipates 0.5 W of power. The demultiplexer chip has 400 gates and dissipates 0.75 W. Performance of these devices compares well in both speed and power to the best gallium-arsenide results reported to date.<
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