Boron channel-stop design for poly-buffered LOCOS using selective boron segregation

A boron channel-stop compensation technique using a selective polysilicon etch prior to field oxidation is proposed for CMOS isolation technologies which use polysilicon buffered LOCOS. The stress relief polysilicon layer is selectively removed over the n-well field regions which results in additional boron segregation into the growing field oxide while the polysilicon layer is being oxidized over the p-well field regions. The resulting field threshold voltages are increased by as much as 11.6 and 6.4 V for the p-well and n-well MOS capacitors, respectively.<
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