1-Mb memory chip using giant magnetoresistive memory cells

A 1-Mb nonvolatile, nondestructive readout M-R memory chip using elements with Giant Magnetoresistance Ratio (GMR) material has been designed. The chip employs dual redundancy, CMOS drive electronics with minimum gate lengths of 0.8 microns, two metal layers, and a 5-V /spl plusmn/10% power supply. The layout has an area of 0.9 cm sq, and approximately 50% of the chip area is devoted to the memory cell array. The memory chip is designed around 1.4 /spl mu/m/spl times/6.1 /spl mu/m, 80-/spl Omega/ elements using GMR material; the elements are spaced 1.4 /spl mu/m apart. The material is composed of two 50-/spl Aring/ ternary alloy layers separated by 30 /spl Aring/ of copper and has a nominal M-R coefficient of 6.0%. Minimum read signal is /spl plusmn/2.5 mV; sense current is 2.5 mA; work current is /spl plusmn/30 mA; and input and output is 4b wide. The memory employs a new read scheme in which two-phase sensing is employed. The scheme provides a sensitive, stable output and diminishes the array area by a factor of two, at the expense of read access time. The design contains over 700000 transistors and over 2 million memory cells; a prototype 64 K section of this design has been built, but the full design has yet to be constructed on silicon. The design demonstrates that with GMR memory cells, M-R memories can be designed with densities and speeds comparable to dynamic RAM's.<
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