Quantifying the impact of homogeneous metal contamination using test structure metrology and device modeling

Deposition of metallic impurities from HF process solutions has been investigated experimentally and explained theoretically in a qualitative manner. The depositions are shown to be electrochemical in nature in that an oxidation reduction reaction results in metal ions in solution depositing on the wafer as elements with an oxidation state of 0. The theory is only qualitative in that it can only predict which metals will deposit, not how much. Experimentally, simple transmission equations can be determined which relate metallic contamination levels on Si wafer surfaces (atoms/cm/sup 2/) to metal concentration in the solution (ppb). Simple test structures have been fabricated with known amounts of iron and copper contamination in the pregate oxide clean of a 1.25 /spl mu/m CMOS process. Device measurements indicate device degradation in the case of copper, confirming deposition studies that copper deposits from HF solutions. Iron contaminated wafers show no contamination related device effects, in support of theoretical predictions and deposition studies indicating iron does not deposit from HF solutions. The importance and potential usefulness of test structures as homogeneous contamination monitors is illustrated through device modeling of the contamination effects observed in the test structures that can then be used to estimate the effects of such contamination on ULSI circuit performance.<
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