Capacitance calculation of IC packages using the finite element method and planes of symmetry

Finite element techniques are presented for determining the capacitance of three-dimensional interconnection structures. Results are presented for two typical intergrated circuits packages: the plastic leaded chip carrier (PLCC) and the dual in-line package (DIP). The symmetry of the capacitance matrix in the package is described and a set of formulas is presented to take advantage of this symmetry in capacitance calculation. This leads to the reduction in CPU time and memory usage and better converged solution.<
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