Reference plane parasitics modeling and their contribution to the power and ground path "effective" inductance as seen by the output drivers

Modeling of the current distribution in package reference (power and ground) planes and the extraction of the associated parasitics are presented. Electrical network and equivalent circuit are developed to model the chip-package interface including the effects of V/sub DD//V/sub SS/ planes. For single- and multichip packages, methods of calculating the "effective" inductance (L/sub eff/) as seen by the output drivers from their on-chip V/sub DD/ and V/sub SS/ buses to the tip of the package pin are explained. Variations from the conventional method (where all connections are assumed identical) of calculating L/sub eff/ are analyzed. Closed-form equations are given to estimate the simultaneous switching noise (SSN) on the on-chip V/sub DD//V/sub SS/ buses for packaged CMOS circuits. The contribution of reference plane (with and without perforation) parasitics on the SSN are investigated. Optimal package pin placement to minimize the plane inductance is discussed.<
>