A low-noise gate structure for DMOS monolithic devices

The effect of gate topology on the device noise figure of silicon double-diffused metal oxide semiconductor (DMOS) field-effect transistors is demonstrated and gate structures for DMOS devices with a noise figure approaching 1 dB at 500 MHz are presented. An analytical model for the output noise power and noise figure is given. The model is based on the assumptions that the device channel noise power spectrum is not correlated to the gate resistive noise and that the frequency is low enough so that the distributed effects of the gate structure are not significant. From this model, it is predicted that a large gate width is necessary for optimum low-noise performance.<
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