Security and performance optimization of a new DES data encryption chip

The implementation of a high-performance data encryption standard (DES) data encryption chip is presented. At the system design level, cryptographical optimizations and equivalence transformations lead to a very efficient floorplan with minimal routing, which otherwise would present a serious problem for data-scrambling algorithms. These optimizations, which do not compromise the DES algorithm nor the security, are combined with a highly structured design and layout strategy. Novel CAD tools are used at different steps in the design process. The result is a single chip of 25 mm/sup 2/ in 3- mu m double-metal CMOS. Functionality tests show that a clock of 16.7 MHz can be applied, which means that a 32-Mb/s data rate can be achieved for all eight byte modes. This is the fastest DES chip reported yet, allowing equally fast execution of all four DES modes of operation, due to an original pipeline architecture.<
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