A programmer's view of the 80960 architecture

The 80960 processor integrates many architectural features normally found in RISC (reduced-instruction-set computer) processors with others found in more traditional architectures. The result is a processor providing high performance while presenting few difficulties for either applications or compiler writers. A discussion is presented of the programming model of the 960, including aspects of the instruction set and the register architecture. Techniques for effective use of the 960 from both assembly language and high-level languages are discussed, including the subroutine calling sequence designed for the architecture.<
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