Wafer level detecting of Idd failures in CMOS ASICs using liquid crystal techniques

Simple techniques using liquid crystal and different power-up schemes to locate the failures in CMOS ASICs on the wafer level are described. These techniques are simple and efficient, and are used to locate defects and floating nodes which cause Idd failures at wafer sort. Wafer level defect reduction and prototype debugging are successfully performed on parts in which Idd source location is difficult.<
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