An all implanted self-aligned enhancement mode n-JFET with Zn gates for GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p/sup +/ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p/sup +//n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f
_T
of 19 GHz with an f
_max
of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits.