A BiCMOS low-power current mode gate

A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML.<
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