Realization of fully path-delay-fault testable non-scan sequential circuits

We present a new approach to synthesizing fully path-delay-fault testable non-scan sequential circuits. Two methods are proposed. Given the state transition graph of a finite state machine, one of our methods generates a fully robustly testable circuit while the other method, which may lead to more area-efficient circuits, guarantees robust or validatable non-robust tests for all paths.<
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