A high performance I/O intensive synthesis-friendly sub-micron field programmable gate array family

The authors describe an advanced family of CMOS field programmable gate arrays developed to significantly reduce the gap in performance and I/O count with masked gate arrays. They detail the advancements in architecture and circuitry which allow 125-MHz 16-b counters, 65-MHz general system performance, and 10-ns clock-to-out delays across a family range of 1500 to 10000 'gate array' gates, and under 100 to over 200 I/O pins. To achieve this while still maintaining 100% automatic place and route, several key advancements were required, including a novel I/O architecture combined with a fast direct I/O clock, and a more uniform logic module for improved synthesis and enhanced combinatorial and sequential logic capability. Performance is significantly improved by scaling the antifuse and CMOS technology from 1.2 to 0.8 mu m. The scaled antifuse, with the same size as a 0.8 mu m contact, reduced the RC interconnect delay by over a factor of 2. A chip compiler allows rapid generation of an extensible family from 1500 to 10000 gate-array gates.<
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