Fermilab physics department Fastbus TDC module

A prototype 64-channel Fastbus TDC built at Fermilab is described. The module features a full custom CMOS four-channel gated integrator chip. One level of analog buffering at the inputs is implemented on chip. A four-event-deep output queue at the bus interface allows a high event rate with low dead time. Each channel can record up to two hits per event. With an occupation rate of 10%, the module can operate at 40000 events/s with dead time of the order of 15%. The TDC operates in common stop mode with a full scale of 1 mu s and a resolution of 1 ns. Data compaction and a leading word count format have been implemented. The board is less complex than current designs.<
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