Partial arithmetic/spl minus/algorithms and architectures

This paper proposes a new concept in computer arithmetic and delineates algorithms for addition, subtraction and multiplication. The proposed architecture is capable of performing additions in constant time and multiplication, in time less than in the best known architectures. The internal representation of numbers is called "a+b" and requires two memory words. The paper also discusses special coding multiplication and organization of the multiplier for VLSI implementation.<
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