MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines

Speculative execution and dynamic scheduling are two promising techniques for achieving high performance in superscalar processors. These techniques require a mechanism for maintaining all architecturally visible machine state. The authors examine the performance implications of three common state maintenance mechanisms: the reorder buffer, the history buffer, and checkpointing. They model the execution of the four integer benchmarks from the SPEC89 suite for a variety of maintenance techniques. They report the results of these measurements and their implications with respect to the design of high performance superscalar processors.<
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