Clocked and asynchronous instruction pipelines

Deeply pipelined processors increase the cost of executing conditional branches. Several branch architectures based on both hardware and software techniques have been proposed to reduce this cost. A popular branch mechanism based on software techniques is static branch prediction with delay slot annulling. This mechanism reduces the cost of conditional branches by making delay slots visible in the architecture. Architectural visibility allows the software to exploit delay slots by executing instructions speculatively. The visibility of the delay slots, however, also results in an increase in code size; compilers must find appropriate instructions which can be scheduled into the delay slots. If no "useful" instructions can be found, then nops must be inserted in the delay slot. The authors propose a novel branch architecture called prophetic branches which allows compilers to exploit branch delays, yet could result in only a minimal increase in code size over non-pipelined code. They show that this branch mechanism can be implemented in deeply pipelined processors with only a minor change in the control logic.<
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