LATCHSIM/spl minus/a latch-up simulator in VLSI CAD environment for CMOS and BiCMOS circuits

This paper presents a generalised latch-up simulator LATCHSIM for the design optimization of latch-up free layout configuration in CMOS and BiCMOS VLSI circuits. The core of the algorithm used in LATCHSIM is based on the fundamental principle of charge neutrality and is solved through a graphical approach to predict the entire latch-up trace for any given layout configuration under different operational and environmental conditions. LATCHSIM has been interfaced appropriately with the popular process simulator SUPREM to determine the effect of process variation on latch-up. The paper presents initial lest results of LATCHSIM validated for SCL's 1.2 /spl mu/m salicided double metal CMOS technology.<
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