Layout influenced factorization of Boolean functions

Traditional approaches to designing VLSI circuits for a given Boolean function usually treat logic minimization and layout generation as two separate subproblems which are solved independently of each other. However, actual layout considerations such as transistor placement and the routing strategy are also important factors in determining the cost of a combinational circuit. Our approach tries to factorize Boolean functions in such a way that the corresponding functional cell layout area is minimized.<
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