On testability of differential split-level CMOS circuits

Differential Split-Level (DSL) CMOS logic offers large speed improvement in CMOS circuit techniques. In this paper, the problem of testing DSL circuits is addressed for the first time to the best of our knowledge. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analyzed. It is shown that most of these faults in DSL circuits cannot be deterministically tested by logic monitoring. However, the presence of these faults can be detected by current monitoring.<
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