Two-layer wiring with pin preassignments is easier if the power supply nets are already generated

We examine the constrained via minimization problem with pin preassignments (CVMPP) which arises in connection with hierarchical physical synthesis. Let A be a circuit composed of subcircuits B, C, D,.... Assume that the placement and routing phase together with the 2-layer wiring of the subcircuits, and the placement and routing phase without the 2-layer wiring of A are completed. CVMPP is the problem of finding a 2-layer wiring /spl deltasub A/ of A which is induced by the 2-layer wirings of the subcircuits and which contains a minimal amount of vias on this condition. First, we show that CVMPP is NP-hard. In the case that the wiring of the power supply nets has already been generated we present a polynomial time algorithm solving CVMPP.<
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