A 600 MHz half-bit level pipelined multiplier macrocell

In this paper a high throughput 8/spl times/8 bit multiplier in a 0.8 /spl mu/ CMOS process is described. A novel pipelining technique in NPCPL (normal process complementary pass transistor logic) allows fine grain pipelining with minimal overhead of area and latency. This is in contrast to conventional approaches where highly pipelined designs are constrained by area and latency overhead of pipeline latches. A two-stage full adder is employed in a carry-save array architecture. The 0.95 mm/spl times/0.87 mm multiplier core supports a throughput of 600 MHz with a power dissipation of 0.9 Watt. Since such a high speed clock cannot be routed from the external world, the clock is generated on-chip. The on-chip clock generator ensures generation of non-overlapping clocks under all conditions of process parameter variations. This along with proper design of clock buffers and clock distribution network minimises clock skew to allow high speed clocking.<
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