TWTXBB: a low latency, high throughput multiplier architecture using a new 4/spl rarr/2 compressor

A fast multiplier is an essential component in any high-performance system. Existing fast multiplier architectures, like Wallace Tree architecture, result in irregular layout with a complex interconnection pattern. We propose a new architecture called Tree of Wallace Tree with XORs as Building Blocks (TWTXBB) and offers a 33% improvement in performance over that of the Wallace tree. It is highly regular rendering itself amenable to automatic generation. The multiplier achieves its high-speed from both a new architecture and a logic style called normal process complementary pass transistor logic (NPCPL). The architecture can provide both low latency and high throughput simultaneously. An elegant pipelining scheme can be tailored to this architecture to achieve fine grain pipelining with insignificant overhead of latency and area.<
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