High-density zero suppressor and encoder VME board using field programmable gate array

We describe a 96 bit zero-suppressor and encoder VME board designed for the RPC trigger system of the L3 Forward/Backward Muon detector at CERN. Running at 20 MHz clock frequency, the board processes the elementary 96 bit wide detector pattern in less than one microsecond, storing hit addresses in a FIFO array. Details of the board architecture based on seven XILINX XC3020 LCAs/spl minus/are presented and simulation and preliminary test results are briefly reported.<
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