Modelling and performance analysis of digital baseband processor of the GPS receiver

A global positioning system (GPS) receiver has been modelled and implemented in software. A digital full-time delay lock loop (DDLL) is designed for the pseudorange time delay measurement and a digital phase-locked loop (DPLL) is applied for measurements of the carrier beat phase and Doppler shift. The closed form expressions of the detection and false-alarm probabilities for the code phase acquisition process and the variance of the code phase tracking error for the code phase fine synchronization process are derived. The performance of the modelled static receivers is validated by computer simulations.<
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