A 300-MHz BiCMOS serial data transceiver

A BiCMOS circuit for serial data communication is presented. The chip has phase-locked loops for transmit frequency synthesis and receive clock recovery, serial-to-parallel and parallel-to-serial converters, and encode and decode functions. Since this is a mixed-analog/digital design, and the transmitter and receiver operate asynchronously, many techniques are used to decrease noise coupling. A 1.2 /spl mu/m BiCMOS process allows operation at speeds of 300 MHz along with this high level of system integration, and the chip consumes less than 1 W from a single 5 V supply.<
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