An ATM queue manager with multiple delay and loss priorities

The performances in cell loss, queuing delay, and standard deviation of four different service classes at the output queue on an asynchronous transfer mode (ATM) output-buffered switch are evaluated. An implementation architecture for the queue manager is proposed. The architecture allows all service classes to share the buffer until the buffer is filled up, and then cells with the lowest loss priority start to be discarded, i.e., the so-called push out scheme. The implementation architecture applies the concepts of fully distributed and highly parallel processing. to schedule the cells' departing or discarding sequence. An implemented VLSI sequencer chip can be used to realize a queue manager that deals with multiple delay and loss priorities.<
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