An efficient logic emulation system

The Realizer, a system which automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. The interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds or thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 XC3090 FPGAs for logic. A 32-b CPU datapath has been automatically realized and operated at speed, and demonstrates very good FPGA utilization.<
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