Synthesis on multiplexer-based FPGA using binary decision diagrams

Synthesis methods are presented for multiplexer-based field-programmable gate arrays, (FPGAs) based on binary decision diagrams (BDDs) for speed optimization, and reduced ordered binary decision diagrams (ROBDDs) for area optimization. A direct mapping is performed on the two types of binary decision diagrams. Practical results are given for an exhaustive list of benchmarks. The results show a big improvement compared to library based approaches.<
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