Identification of single gate delay fault redundancies

Gate delay faults can represent the effects of common point faults in logic circuits. A gate delay fault model based on the analysis of these effects in the normal operation of logic circuits is developed. The fault model allows for delay faults of both bounded and unbounded size. Techniques have been developed to identify single gate delay faults that do not have any effect on the normal operation of logic circuits. These techniques are applied to various benchmark circuits and indicate the existence of a surprisingly large number of such redundancies.<
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