Performance-driven synthesis in controller-datapath systems

This paper describes new algorithms which combine state assignment and pipelining to perform timing-driven synthesis. A cycle time requirement for a controller-datapath system must be satisfied under fixed arrival times of datapath outputs and departure times of datapath inputs. As a result, the controller's design must take into account not only cycle time of the FSM in isolation, but also input arrival time specifications and output departure time requirements. Most state assignment methods minimize area; moreover, state assignment alone may not be sufficient to eliminate all delay bottlenecks. Performance-Driven Synthesis (PDS) applies both high-level and sequential optimizations to meet a cycle time requirement: we use new don't-care assignment algorithms to minimize the delays of FSM output signals on critical paths by reducing their dependencies on late-arriving FSM primary input signals; we also use new pipelining algorithms to break critical paths which cannot be fixed by state assignment. Experimental results show that PDS improves delays with little area overhead.<
>