A 600 MHz 100 K ECL output buffer fabricated in 0.9 mu m CMOS

A 600 MHz 100 kbit emitter-coupled logic (ECL) output buffer fabricated in 0.9 mu m CMOS is presented. A new circuit technique is used which dynamically adjusts both the low and high DC drive levels of the output transistor circuit. The high AC performance of the buffer is achieved by segregating the high-speed data flow from the low-speed transistor sizing control bits. This segregation occurs at a pseudo-NMOS gate-like structure which itself is reconfigured by the values of the control bits. Actual measured results of the buffer operating at 677 MHz are given.<
>