200-1200 MHz CMOS techniques

Circuit and design techniques for high speed logic using standard CMOS processing have been developed. Several experimental chips performing real functions at speeds up to 1 GHz are demonstrated. Beyond normal speed improvement methods, two new methods are used. These are (1) a new clocking technique, the true single phase clock, and (2) transistor sizing using a new optimizer tool, SLOP (Switch Level Optimizer Program). Extensions of these methods are discussed.<
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