A simple machine (based on the SK-combinator reduction mechanism)

A simple machine architecture based on an extension to the combinator notation is described. Code travels along a unidirectional stream and is executed in parallel by simple finite state machine based cells separated by sections of a first-in, first-out (FIFO) buffer. The resulting regularity and structural simplicity ensure a good match to VLSI implementation. It is verified that the extended combinator is a viable execution model. Preliminary simulation results are presented.<
>