An efficient modeling and synthesis procedure of asynchronous sequential logic circuits

A model and procedure are developed for synthesizing asynchronous sequential logic circuits (ASLCs). This model represents the functional behavior with a more compact form and the procedure can synthesize them more efficiently than the traditional one. With the identification of edge inputs from the design specification, a set of equations can be generated which describes the functional behavior of the logic module. The calculated states from these equations can easily be mapped onto an n-cube to obtain a race-free assignment. Further delineation of mode inputs and level inputs from data inputs facilitates the process of decomposing complex logic functions into smaller ones which can be more easily synthesized.<
>