Advanced delay analysis method for submicron ASIC technology

A new ASIC delay analysis method is presented, in which a two-dimensional delay table model is used for cells and the tailored circuit simulation is used for wires. Input waveform slope and load capacitance play important roles in the variation of cell delay. In the case of an arbitrary RC tree load, the equivalent load capacitance is calculated by using a node reduction technique and the proposed equation. This model preserves accurate delay estimation, typically within 3% compared to that of HSPICE.<
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