Evaluating VHDL-based ASIC synthesis tools

An evaluation of VHSIC hardware description language (VHDL) based design tools using synthesis vs. schematic capture-macrocell approach to field programmable gate array (FPGA) design is described. The risk of committing to an ASIC technology for a project that may or may not go into production can be mitigated by using FPGAs. Designing with VHDL allows flexibility if the decision is made to migrate the design.<
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