A comparison of processor topologies for a fast trainable neural network for speech recognition

A fast processing system is necessary to provide adequate learning speed in multilayer neural networks (NNs). Some schemes for mapping from a multilayer NN to a parallel digital processor topology are discussed. For a mesh topology there exists an optimal point where the computation count is minimum. In order to allow for applications such as a speaker-independent speech recognizer, the authors extend this mesh architecture to operate on sequential or, specifically, spatio-temporal inputs. A pipelining scheme is thus revealed, making it possible to improve the processing throughput. An extension of the processing element structure is obtained by introducing dynamic neurons and a consequent pipelining architecture.<>