VLSI design of dynamically reconfigurable array processor-DRAP

A novel 2-D bidirectional, reconfigurable systolic array is presented. The system can be easily reconfigured and applied in many DSP and matrix processing applications. The different interconnection schemes are achieved by a set of simple local switches that contributes only a 15% increase in the chip area. The processor was implemented in 2- mu m CMOS technology and was tested for 1-D linear, 2-D square-mesh, and 2-D hexagonal structures. Another feature of this system is that its configuration patterns can be expanded to support additional algorithms.<
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