Generic ASIC architecture and synthesis scheme for DSP

A description is given of the architectural ideas underlying a high-level IC design tool under development, which is intended specifically for digital signal processor (DSP) users. Although by necessity more restrictive than a general-purpose ASIC design system, this tool is able to support the rapid specification and verification of dedicated DSP processors of arbitrary throughput, accuracy, and functional complexity. The tool maps applications on to a generic pipelined numerical processing architecture, which is flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. An intelligent defaults system provides further leverage by accepting incomplete specifications and filling in the blanks. The architectural approach is illustrated by a 2-D video-rate discrete cosine transform case study.<
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