A single chip adaptive QAM processor for data rates up to 500 Mbit/s

The miniaturization of CMOS structures allows the realization of a complex-valued adaptive time domain equalizer at a symbol rate of 30 MHz on one VLSI chip by using the 'application specific' gate array technique (ASICs). By making use of a full custom design and CMOS technology it was possible to integrate on one chip not only an entire complex-valued baseband transversal equalizer but also all the important hardware needed to perform the digital signal processing functions of a typical QAM receiver used for high capacity digital radio. The chip application covers 16 QAM(TCM) to 1024 QAM(TCM) and it can be operated with a maximum symbol speed of 60 MBaud. It comprises an adaptive time domain equalizer, a frequency domain slope equalizer, the digital parts of timing and carrier recovery loops, FM interference suppressor and some useful housekeeping functions (offset control, AGC). It can also be used for crosspolarization interference cancellation (XPIC).<
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