A two-level pipelined systolic array chip for computing the discrete cosine transform

A two-level pipelined systolic array chip for the discrete cosine transform (DCT) is presented. This chip is based on a new memory-based systolic algorithm which not only uses small ROMs and adders to realize the multiplications but also owns good data locality. Therefore, this chip possesses outstanding performance in hardware cost, computing speeds, the number of I/O channels, and the I/O bandwidth.<
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