A 10-b 100-Msample/s pipelined subranging BiCMOS ADC

A 10-b 100-Msample/s pipelined subranging analog-digital converter (ADC) has been achieved. Such technologies as a pipelined subranging scheme, a track-and-hold amplifier (THA) with current-switching sampling gates, a 94-dB dc open-loop gain, a 335-MHz unity-gain frequency op amp, and a carry-look-ahead adder for digital error correction are presented. The 3.4-mm*5.6-mm ADC chip was fabricated using a 0.8- mu m BiCMOS process and operates with 950-mW power dissipation from a single -5-V power supply.<
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