Piezoelectric microphone with on-chip CMOS circuits

An IC-processed piezoelectric microphone with on-chip, large-scale integrated (LSI) CMOS circuits has been designed, fabricated, and tested in a joint, interactive process between a commercial CMOS foundry and a university micromachining facility. The 2500*2500*3.5 mu m/sup 3/ microphone has a piezoelectric ZnO layer on a supporting low-pressure chemical-vapor-deposited (LPCVD), silicon-rich, silicon nitride layer. The optimum residual-stress-compensation scheme for maximizing microphone sensitivity produces a slightly buckled microphone diaphragm. A model for the sensitivity dependence of device operation to residual stress is confirmed by applying external strain. The packaged microphone has a resonant frequency of 18 kHz, a quality factor Q approximately=40, and an unamplified sensitivity of 0.92 mV/Pa. Differential amplifiers provide 49 dB gain with 13 mu V A-weighted noise at the input.<
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