A physical-based analytical model for hot-carrier induced saturation current degradation of p-MOSFET's

The delay time of a CMOS inverter is directly related to the p-MOSFET saturation current. An accurate aging model for the saturation current is essential for the modeling of the CMOS inverter degradation. In this paper, we report that the saturation current degradation proceeds logarithmically in stress time. A physical analytical model, based on the pseudo-two-dimensional model, is derived for the first time to describe the saturation current degradation under various stress and measurement conditions. There are no empirical parameters in the model. Two physical parameters, the capture cross section and the density of states of electron traps, can be determined independently from the measured degradation characteristics. The simple expression is highly recommended for the modeling of the degradation of the digital CMOS circuits.<
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