A high-power GaAs FET having buried plated heat sink for high-performance MMIC's

This paper reports an FET structure, named "Advanced SIV FET" (advanced source island via-hole FET). The developed structure contains a selectively formed buried PHS (plated heat sink) instead of having thick backside gold metal. In this FET, the thickness of the substrate under the active layer, which produces heat during operation, is set to be 30 /spl mu/m with a buried 70 /spl mu/m thick gold plated heat sink for achieving low thermal resistance, and the thickness of other portion of the chip is set to be 100 /spl mu/m for low loss in microstrip lines and sufficient mechanical strength. This FET structure has provided higher power output and power added efficiency with great simplicity of wafer and chip handling. The experimental results have shown that an FET, of 1350 /spl mu/m gate width, has achieved a superior low thermal resistance of 16/spl deg/C/W corresponding to a maximum channel temperature of 42.1/spl deg/C. RF performances, at V/sub ds/=7 V, show a power output as high as 27.9 dBm with a power added efficiency of 32% at the 1 dB power compression point and a linear gain of 8.3 dB all at 18 GHz. It also has achieved an excellent power density of 0.54 W/mm at V/sub ds/=8 V. This structure has shown mechanical reliability which conforms to MIL-STD-883.<
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