A loop-based built in self test strategy for ASIC design

A method is described for including built-in self-test (BIST) in digital application-specific integrated circuits (ASICs). All the general logic (i.e., nonmemory parts) of an ASIC is tested as a single partition of interconnected self-test loops. The loops are based on simple, regular test structures and perform simultaneous test pattern generation and response compaction. The occurrence of fault masking due to local register interdependence is minimized by using special shift-register macros. The BIST method has been successfully implemented in a 17K gate-equivalent ASIC, for which a general logic fault coverage of 92% is achieved after only 166 test cycles.<
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