The Astronautics ZS-1 processor

The Astronautics ZS-1 is a high speed minisupercomputer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture which splits instruction words into two streams, one for fixed-point/memory-address computation and the other for floating-point operations. The two instruction streams are then processed in parallel, with architectural queues providing communication between the streams. Pipelining is used extensively throughout the ZS-1. The combination of decoupling and pipelining provides overall, sustained performance of about one third a CRAY-XMP-1 on compiled double-precision Fortran. The authors give a description of the decoupled architecture and discuss other forms of parallelism used in the ZS-1. A discussion of static and dynamic instruction scheduling is also included.<
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